1. Field of the Invention
The present invention relates generally to processors, and in particular to methods and mechanisms for reducing memory latency in the presence of barrier instructions.
2. Description of the Related Art
In modern day processors, instructions may be executed out of order. This may improve processor performance, but it may also result in unintended behavior. For example, in some cases a programmer may intend for specific sequences of instructions to execute in order, but if the processor reorders these instructions this may result in unwanted errors. Therefore to avoid these errors, the programmer may insert barrier commands in the code to enforce a particular instruction ordering. A barrier is an instruction that has a property such that instructions that the barrier controls must not be reordered with respect to the barrier. Therefore, the barrier can be inserted into a stream of instructions to prevent some instructions from being executed before other instructions.
When a memory barrier is encountered in the code, any younger memory access instructions will be delayed until the memory barrier completes. When the memory barrier completes, the delayed memory accesses may be restarted and allowed to proceed to memory now that the barrier is finished. If these restarted memory accesses miss in the cache closest to the processor core, the memory accesses may then access the next level of cached memory, or even main memory itself. As a result, the latency of the next level memory will be exposed to the processor, essentially degrading performance of running applications due to the stalls encountered when waiting on memory.